The invention relates to an integrated circuit, comprising driving means connected to a bit-line and a non-bit line. The invention also relates to an integrated field-effect transistor memory circuit comprising memory cells which are arranged in rows and columns, each column of memory cells being connected to a bit line and a non-bit line by way of selection means. The integrated circuits or integrated field effect transistor memory circuits to which the invention relate also comprise at least one sense amplifier which comprises a first and a second input for coupling to the bit line and the associated non-bit line, which sense amplifier performs a current measurement on the first and the second input during the reading of information on the first and the second input.
A memory circuit of this kind is known from the article "Design tricks speed up INMOS's SRAMS" in "Electronics", Apr. 16, 1987, p. 34. The cited article describes a memory circuit in which a sense amplifier senses and amplifies the information on bit lines by detection of current instead of detection of voltage differences. Consequently, the processing speed of such a sense amplifier is substantially independent of the parasitic bit line capacitance, so that a memory design may be simpler. However, the cited article gives no details on how a suitable sense amplifier can be realized in a simple circuit.